n-channel jfet monolithic dual sst404 / sst405 / sst406 features very low noise . . . . . . . . . . . . . e n < 10 nv/ hz @ 10hz low input bias . . . . . . . . . . . . . . . . . . . . . . . . . . . i g < 2pa high breakdown voltage. . . . . . . . . . . . . . . . . . . b v > 50v applications precision instrumentation input amplifiers impedance converters description the sst404 series is a very low noise monolithic n-channel jfet pair in a surface mount so-8 plastic package. designed utilizing calogics propriet ary jfet processing techniques these devices are ideal for front end amplification of low level signals. the low noise, low leakage and good frequency response are excellent features for sensitive medical, instrumentation and infrared designs. ordering information part package temperature range sst404-6 plastic so-8 -55 o c to +125 o c note: for sorted chips in carriers, see u401 series pin configurations llc so-8 top view (1) s1 (2) d1 (3) g1 (4) n/c n/c (8) g2 (7) d2 (6) s2 (5) cj2 product marking sst404 r04 sst405 r05 sst406 r06
sst404 / sst405 / sst406 llc absolute maximum ratings (t a = 25 o c unless otherwise noted) parameter/test condition symbol limit unit gate-drain voltage v gd -50 v gate-source voltage v gs -50 v forward gate current i g 10 ma power dissipation (per side) p d 300 mw (total) 500 mw power derating (per side) 2.4 mw/ o c (total) 4 mw/ o c operating junction temperature t j -55 to 150 o c storage temperature t stg -55 to 200 o c lead temperature (1/16" from case for 10 seconds) t l 300 o c electrical characteristics (t a = 25 o c unless otherwise noted) symbol characteristcs typ 1 sst404 sst405 sst406 unit test conditions min max min max min max static v (br)gss gate-source breakdown voltage -58 -50 -50 -50 v i g = -1 m a, v ds = 0v v (br)g1 - g2 gate-gate breakdown voltage -58 50 50 50 i g = 1 m a, v ds = 0v, v gs = 0v v gs(off ) gate-source cut off voltage -1.5 -0.5 -2.5 -0.5 -2.5 -0.5 -2.5 v ds = 15v, i d = 1na i dss saturation drain current 2 3.50.5100.5100.510 ma v ds = 15v, v gs = 0v i gss gate reverse current -2 -25 -25 -25 pa v gs = -30v, v ds = 0v -1 na t a = 125 o c i g gate operating current -2 -15 -15 -15 pa v dg = 15v, i d = 200 m a -0.8 -10 -10 -10 na t a = 125 o c r ds(on) drain-source on-resistance 250 w v gs = 0v, i d = 0.1ma v gs gate-source voltage -1 -2.3 -2.3 -2.3 v v dg = 15v, i d = 200 m a v gs(f) gate-source forward voltage 0.7 ig = 1ma, v ds = 0v dynamic g fs common-source forward transconductance 1.5 121212 ms vdg = 15v, i d = 200 m a f = 1khz g os common-source output conductance 1.3 2 2 2 m s g fs common-source forward transconductance 1.5 272727 vds = 10v, v gs = 0v f = 1khz g os common-source output conductance 10 20 20 20 c iss common-source input capacitance 8 8 8 pf v dg = 15v, i d = 200 m a f = 1mhz c rss common-source reverse transfer capacitance 1.5 3 3 3 e n equivalent input noise voltage 10 20 20 20 nv/ hz v dg = 15v, i d = 200 m a f = 10hz matching | v gs1 - v gs2 | differential gate-source voltage 15 20 40 mv v dg = 10v, i d = 200 m a d | v gs1 - v gs2 | d t gate-source voltage differential change with temperature 25 40 80 m v/ o c t a = -55 to 25 o c v dg = 10v, i d = 200 m a 25 40 80 t a = 25 to 125 o c cmrr common mode rejection ratio 102 95 90 db v dg = 10 to 20v, i d = 200 m a notes: 1. for design aid only, not subject to production testing. 2. pulse test; pw = 300 m s, duty cycle 3%.
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